A Global Maximum Error Controller Based Nonlinearity Aware TPWL Method for Reducing Nonlinear Systems

Abstract

Model order reduction is a common practice to reduce large order systems so that their simulation and control become easy. Nonlinearity aware trajectory piecewise linear is a variation of trajectory piecewise linearization technique of order reduction that is used to reduce nonlinear systems. With this scheme, the reduced approximation of the system is generated by weighted sum of the linearized and reduced sub-models obtained at certain linearization points on the system trajectory. This scheme uses dynamically inspired weight assignment that makes the approximation nonlinearity aware. Just as weight assignment, the process of linearization points selection is also important for generating faithful approximations. This article uses a global maximum error controller based linearization points selection scheme according to which a state is chosen as a linearization point if the error between a current reduced model and the full order nonlinear system reaches a maximum value. A combination that not only selects linearization points based on an error controller but also assigns dynamic inspired weights is shown in this article. The proposed scheme generates approximations with higher accuracies. This is demonstrated by applying the proposed method to some benchmark nonlinear circuits including RC ladder network and inverter chain circuit and comparing the results with the conventional schemes.     

Vitamin D Compounds PRI-2191 and PRI-2205 Enhance Anastrozole Activity in Human Breast Cancer Models

1,25-Dihydroxycholecalciferol, the hormonally active vitamin D₃ metabolite, is known to exhibit therapeutic effects against breast cancer, mainly by lowering the expression of estrogen receptors and aromatase activity. Previously, the safety of the vitamin D active metabolite (24R)-1,24-dihydroxycholecalciferol (PRI-2191) and 1,25(OH)₂D₃ analog PRI-2205 was tested, and the in vitro activity of these analogs against different cancer cell lines was studied. We determined the effect of the two vitamin D compounds on anastrozole (An) activity against breast cancer based on antiproliferative activity, ELISA, flow cytometry, enzyme inhibition potency, PCR, and xenograft study. Both the vitamin D active metabolite and synthetic analog regulated the growth of not only estrogen receptor-positive cells (T47D and MCF-7, in vitro and in vivo), but also hormone-independent cancer cells such as SKBR-3 (HER-2-positive) and MDA-MB-231 (triple-negative), despite their relatively low VDR expression. Combined with An, PRI-2191 and PRI-2205 significantly inhibited the tumor growth of MCF-7 cells. Potentiation of the antitumor activity in combined treatment of MCF-7 tumor-bearing mice is related to the reduced activity of aromatase by both An (enzyme inhibition) and vitamin D compounds (switched off/decreased aromatase gene expression, decreased expression of other genes related to estrogen signaling) and by regulation of the expression of the estrogen receptor ERα and VDR.     

PSO优化多核RVM的模拟电路故障预测

针对模拟电路健康管理的特点，提出了一种基于PSO优化多核RVM的模拟电路故障预测方法。利用参数分析得到电路的输出频域响应作为特征，计算其与电路无故障标准响应的欧氏距离来表征电路元件健康值，将多个核函数线性组合，并用PSO优化多核RVM参数后的模型实现对各个时间点元件的健康值变化轨迹进行预测。仿真结果表明，该方法在小样本情况下，预测效果优于单一核函数的RVM模型，适用于健康管理中实时预测，具有较好的实用性。     

一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

继电保护中多路模拟量采集系统的设计

介绍了一种基于高性能浮点DSP芯片TMS320C32、CPLD芯片XC95288和A/D采样芯片AD976组成的多路采集系统的工作原理以及设计方法。通过对第一路施加特殊的电压量,在CCS开发环境下读取采样缓冲区的值,并利用Matlab对采样数据进行了全波傅氏变换。此外,该系统已在继电保护中得到广泛应用,实践表明,该系统能较好地解决多路模拟量的采集,并确保了采样数据的安全可靠性。     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

中英班"电路"双语教学初探

在对中英班电路课程实施双语教学的基础上，探讨了电路课程双语教学的摹本原则。首先应明确课程目标和了解学生特点，应该选择优秀原版教材并深入研究其教学思想和教学方法。在教学实施过程中，采用灵活多样的教学方案，不仅创造学英语，用英语的教学氛围，也将先进的教育思想和学习方法传授给学生。对学生反馈信息的分析表明，电路课程的双语教学取得了较好的效果。最后指出了存在的问题及进一步努力的方向。     

Implementing Qubits with Superconducting Integrated Circuits

Superconducting qubits are solid state electrical circuits fabricated using techniques borrowed from conventional integrated circuits. They are based on the Josephson tunnel junction, the only non-dissipative, strongly non-linear circuit element available at low temperature. In contrast to microscopic entities such as spins or atoms, they tend to be well coupled to other circuits, which make them appealling from the point of view of readout and gate implementation. Very recently, new designs of superconducting qubits based on multi-junction circuits have solved the problem of isolation from unwanted extrinsic electromagnetic perturbations. We discuss in this review how qubit decoherence is affected by the intrinsic noise of the junction and what can be done to improve it. PACS: 03.67.-a, 03.65.Yz, 85.25.-j, 85.35.Gv     

Synchronous Full-Scan for Asynchronous Handshake Circuits

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.